3657 Country Meadow Lane · Escondido, CA 92025                          Hm 760-233-2903                      Cell: 858-254-0008

Email: mladenik@roboticdeathcompany.com

 

OBJECTIVE

Seeking a contract/consulting position utilizing my experience in circuit design for work in a very dynamic high tech environment.

 

EDUCATION

CALIFORNIA STATE POLYTECHNIC UNIVERSITY, Pomona, CA                                                                MSEE., June 1987

Emphasis in Communications Systems.

Thesis: Adaptive Notch Filter For Use In A Spread Spectrum Communication Systems.

 

PURDUE UNIVERSITY, West Lafayette, Indiana                                                                                            BSEE, May 1982

 

EXPERIENCE

Senior Hardware Consultant AP Labs, San Diego, CA                                                                              June 2007– Present

Designed a managed 5 Port Gigabit Ethernet Switch card for use in commercial aircraft wireless communication system.  The Switch chip was a Broadcom BCM5397 and the Management processor was an ATMEL AT91SAM9260 and thr board had 256MB of SDRAM and 256MB of NAND FLASH.  The board has a Lattice LC4064V CPLD to perform some glue and custom function required.

 

Senior Hardware Consultant Windriver, San Diego, CA                                                                           Aug 2006 – June 2007

Designed the Sensor and User Interface Boards used in a 12M Pixel Digital Video Cinema Camera.  The sensor board design had 6 programmable Current Sources and one programmable current sink.  The 12M Pixel CMOS Video sensor has 200 differential data outputs that run at 200MHz.  I also did a complete system timing analysis for the data that came from the Sensor Board through cables to the Video Processor board and into a Xilinx FPGA.  The user interface board has push buttons(all debounced in hardware), Real Time Clock RTC, Rotary encoder, LCD and backlight control.  The entire board is controlled using I2C interface.  The rotary encoder, as well as other miscellaneous glue functions, is implemented in a Xilinx CPLD.

 

Senior Hardware Consultant A2E Technology, San Diego, CA                                                               Jul 2006 – Nov 2006

Designed an MP3 player development platform using a sigmatel MP3 chip set.   Developed user interface boards using Cypress PSoC chips to incorporate CapSense button technology

 

Senior Hardware Consultant Daylight Solutions, Poway, CA                                                  Nov 2005 – Aug 2006

Designed a Front Panel and Motions Board used to control a scannable infared laser device.  The Motion Board is a Motorola Coldfire Based board with a Xilinx FPGA.  The Front Panel board has  XIlinx CPLD to perform all the functions on the board.

 

Senior Hardware Consultant TDG Aerospace, Escondido, CA                                                               April 2003 – Nov 2005

Designed a 3 phase protection device to protect fuel pumps on commercial aircraft.

 

Senior Hardware Consultant, Cymer Lasers, San Diego, CA                 Jul 2002– April 2003 and Jan 2006 – Jun 2006

Wrote Verilog for FPGA,s debugged hardware, wrote test procedures, and facilitated Cluster Interface boards through the productions process.   Took over project for Engineer who left and wrote test procedures, debugged boards, facilitated all the paperwork to get the unit into production. Simulated and redesign analog channels and re-spun boards for reliability.

 

Senior Hardware Consultant, Fiberyard, San Diego, CA                                                                          Apr 2002– Aug 2002

Successfully fixed bid a CPLD design.  The CPLD was the interface between motion processors and a number of ADC’s & DAC’s.  Designed, documented, simulated and debugged all within schedule.

 

Senior Hardware Consultant, Copper Mountain Networks, San Diego, CA                                         May 2001– Mar 2002

Lead Hardware Design on a SONET OC3 WAN Board.  This board had Power PC 850 Controller system, PMC OC3 framer, Dual 10B-2 Ethernet, dual 1.25 Serial backplane interface, a FPGA to implement the Utopia Level 2 interface, and four OC3 Optical transceivers.  Also in charge of debugging and correcting problems on an Octal T1/E1 IMA WAN Board.  This board was debugged and re-spun successfully for 1st article production.

 

Project Manager, Robotic Death Company, Escondido, CA www.roboticdeathcompany.com      Dec 2001– Present

Project manager for a Nationally recognized combat robot team.  Was involved with the design and construction of over 12 fighting robots ranging in size from an ant weight (16 Oz), to a super heavyweight (340 Pounds).  Four of the robots won championships and one won the National championship while two others took 2nd in the country.

 

Senior Hardware Consultant, Stonefly Networks, San Diego, CA                                                         Dec 2000 – May 2001

Fibre Channel Architecture study for layer 4 Fibre Channel switch.

 

Senior Hardware Consultant, Sensoria, San Diego, CA                                                                           April 2000 – Dec 2000

Developed IDB-C, ACP & IEEE-1394 solutions for use in Automobiles.  Wrote C code to test boards.  Integrated high level cores using Verilog in a Xilinx Spartan FPGA. 

 

Senior Hardware Consultant,  System Design Group, San Diego, CA                                  Jun 1999 – May 2000

Designed a Windows CE laptop computer using the INTEL StrongARM processor.  This laptop is used to control robots in an industrial manufacturing environment.  Designed an ASIC test board for Agilent Digital Camera ASIC’s.

Senior Hardware Engineer PRISA Networks, San Diego, CA                                                                   Oct 1996 – Jun 1999

ORCA FPGA using VHDL, for use on a PCI-64 Dual Fibre Channel board.  The FPGA runs at 40 MHz has over 30K gates and 315 I/O's.  This board has data throughputs of over 1 GBPS per channel

 

Senior Hardware Consultant, logi-core Design Consulting Group, San Diego, CA                            Nov 1997 - Mar 1998

ALTERA FPGA using VHDL that precisely controls the number and frequency of pulses that are used to control a stepper motor.

 

Senior Hardware Consultant, ITEC (Formerly PCPI), San Diego, CA                                                     Sep 1996 - Nov 1997

Designed multiple Ethernet and Appletalk Interface Cards plug in boards for various Laser printers.  I successfully fixed bid 2 designs for this company.

 

Senior Hardware Consultant, Code-A-Rama Inc., Longmont, CO                                                          Sep 1996 – Feb 1997

Designed a Multi-Function I/O card that had USB, Appletalk, SCSI, and a RS232 interfaces.  This entire design was completed through telecommuting and was fixed bid.

 

Senior Digital Design Consultant, Doctor Design Inc., San Diego, CA                                   Jul 1995 - Oct 1996

Worked on the design of a high speed Fibre Channel network card that plugs into Silicon Graphic workstations. This card has a data throughput of 1 GBPS.  Designed two 40Mhz designs, one using an ALTERA FPGA and one using an ALTERA EPLD.

 

Senior Electronics Engineer, TV/COM International, San Diego, CA                                                       Sep. 1993 - Jul 1995

High-speed designs (Up to 60Mhz) include using FPGA (Quicklogic), CPLD (Lattice, AMD, Cypress), PAL, and microprocessor (M68340), Proficient with OrCad, Viewlogic, ABEL, CUPL, PALASM and Quicklogic design tools.  Designs include a high speed Variable Rate Digital Filter used for data recovery on a high-speed modem.  Also designed the Service Module, which is the main board in the Integrated Receiver Processor (IRP).  This board accepts MPEG2 digital data from a receiver and demultiplexes the digital Video into digital audio and video and outputs analog video and audio.

 

Senior Electronics Engineer, Loral Conic, San Diego, CA                                                                        Feb 1990 – Sep 1993

Have taken all of my designs from concept to test and through production with minimal technical problems. Designed the digital interface to a RF transceiver.  This design included a 4M byte buffer CRC generate and verify, frame sync and generation. This design contains 2 Actel Field Programmable Gate Arrays (FPGAs), which were designed and simulated using Viewlogic software CAD system.  Designed and developed embedded encryptors and decryptors for use in Loral’s space transponders.  Lead design engineer on a data Encryption/Decryption module that is controlled with an 87C51FB Microcontroller. The module has circuitry for battery backup switchover and power glitch protection.  The complete system contains 5 PC boards, which include four Actel FPGAs and one PAL. The module was designed with tried and tested rules that enabled it to fully pass all required Tempest testing.  The FPGAs were designed and simulated using Viewlogic software CAD system. Designed the tester and test procedure for this system and assisted the customer with integration, troubleshooting, and testing.

 

Senior Electronics Engineer, General Dynamics, Electronics Div., San Diego, CA                             Oct 1986 – Feb 1990

Hardware design and test of digital and analog circuits used for narrow band signal demodulation. Successfully designed and tested a programmable second order digital Phase Lock Loop circuit used for clock and data recovery.  Also designed and tested analog and digital circuits in an 8086/8087 controlled signal processor within a passive radar system.  This included some machine code software development to test out specific hardware functions of the system.

 

Electronics Engineer, General Dynamics, Pomona Div., Pomona, CA                                                   Sep 1984 – Apr 1986

 

Electronics Engineer, Fleet Analysis Center, Missile Systems Effect. Div. Corona, CA                       Jun 1982 - Sep 1984

 

TECHNICAL SKILLS

Extensive knowledge of engineering design principals, design practices, and design factors.

Proficient in Verilog, VHDL, AHDL (ALTERA Maxplus 2), C Language, ABEL HDL, OrCad, Viewlogic, Exemplar, Model Tech, Synario, Quicklogic Tools, Timing Designer, Keil C Compiler.

 
CLEARANCES

      Previously held DOD Secret and Comsec, DOD Top Secret, SBI, EBI (with poly), and others.

 

REFERENCES

Patricia Klaus       Patricia.Klaus@windriver.com         (858) 824-4310

Dan Fish               defish1@cox.net                                  (858) 472-3785

Blaine Readler     blaine@dpde.com                              (858) 613-0440

Bob Kirstein          rkirstein@stratusengineering.com  (858) 663-1841

Mark Elliott            elliottx@cox.net                                    (619) 322-8185

John Neilson        agsma@cox.net                                  (619) 561-2485

 

More references can be furnished upon request.